Masanao Yamaoka
Department Manager, HITACHI


A new computing architecture, a CMOS annealing machine, to solve combinatorial optimization problems


A new computing architecture, an annealing machine, is proposed. The annealing machine maps combinatorial optimization problems into an Ising model and solves the problems by its own convergence property.Several implementations of the annealing machine are proposed. One is a quantum annealing machine using superconductor devices. The other implementation is using optical devices and calculate the Ising model. We proposed a CMOS annealing machine, which is a ASIC/FPGA CMOS implementation of the annealing machines. We constructed prototypes of the CMOS annealing machine. The 1st generation prototype with ASIC implementation, the 2nd generation prototype with FPGA implementation and the card-size prototype with 2-chip ASIC implementation are used to confirm its ability to solve combinatorial optimization problems and its high energy efficiency. The 2nd and card-size prototypes also confirm its multiple-chip operation, which enables a higher scalability of the CMOS annealing machine solving large size optimization problems.


Masanao Yamaoka received the B.E., M.E., and Ph. D degrees in electronics and communication engineering from Kyoto University, Kyoto, Japan, in 1996, 1998, and 2007, respectively. In 1998, he joined the Central Research Laboratory, Hitachi, Ltd., Tokyo, Japan, where he was engaged in the research and development on low-power embedded SRAM and CMOS circuits. Since 2012, he has been engaged in the research of new-paradigm computing using CMOS circuits.

Please note that in-person conferences (i.e. AI Hardware Expo on May 5th-6th 2020, AI Enterprise Expo on August 25th-26th 2020 and AI Robotics Expo on November 12th-13th 2020 at SEMI, Milpitas, Silicon Valley) are converted into this virtual AI Expo series.